

## 2020 Bavikadi [A Review of In-Memory Computing Architectures for Machine Learning Applications](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5131/GLS_IMC20.pdf)

![aa](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5142/prominent.PNG 'aaaa')

- architectures

> DRAM stores data capacitively which requires frequent refreshing, making the logic operations timing sensitive. 

> SRAM is limited by the comparatively lower cell density and energy efficiency. 

> ReRAM suffers from high write latency and

> **STT-MRAM suffers from high error rate due to fluctuations in ohmic properties of the cells**

![ll](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5141/architectures.PNG 'll')

> Magnetic memories (STT-MRAM/SOT-MRAM), especially multi-level cell MRAMs (MLC-STT) can be expected to achieve more popularity as IMC platform **due to their non-volatility as well as a wider functionality range compared to DRAM and SRAM**

## 2019 Bing Li [An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications](https://arxiv.org/pdf/1906.06603.pdf)

![x](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5134/sram%2Bdram%2Benm.PNG 'x')

- all processors attempted before 2020

![ff](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5140/table%2Bof%2Ball.PNG 'f')



## 2020 Amirali Amirsoleimani [In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives](https://onlinelibrary.wiley.com/doi/epdf/10.1002/aisy.202000115)

![qq](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5138/challenges.PNG 'qq')

- spider diagrams

![yy](https://knowen-production.s3.amazonaws.com/uploads/attachment/file/5139/spider.PNG 'yy')

This kind of binary memory could **combine high switching speed (sub-ns), low energy (pJ range), and high endur-ance ($10^{12}$ cycles) of DRAM and SRAM with non- volatility (>10 years retention) and scalability (<10 nm)** 