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Dmitri Nikonov

Created about 5 years ago, updated 29 days ago

2019 Benchmarking Delay and Energy of Neural Inference Circuits DMITRI E. NIKONOV

Supplementary Materials for “Benchmarking Delay and Energy of Neural Inference Circuits”

A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across
several application cases. Promising architecture/device combinations are identified.

Beyond CMOS computing with spin and polarization Sasikanth Manipatruni, Dmitri E. Nikonov    and Ian A. Young

2018 Hybrid Piezoelectric-Magnetic Neurons: A Proposal for Energy-Efficient Machine Learning William Scott

Shannon-inspired Statistical Computing to Enable Spintronics

  • Voltage and Energy-Delay Performance of Giant Spin Hall Effect Switching for Magnetic Memory and Logic Sasikanth Manipatruni

Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition DMITRI E. NIKONOV

Intel

13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Techniquegood MRAM?

https://www.techspot.com/news/78859-intel-confirms-non-volatile-mram-produced-high-yield.html

https://www.eetimes.com/intel-says-finfet-based-embedded-mram-is-production-ready/

Parents

  • Analog - coupled oscillators
  • Digital Parallel Computing Architecture - NeuroSim+
  • Intel

Children

  • Basic physics parameter for switching&dissipation

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