Digital Parallel Computing Architecture - NeuroSim+

2019 MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations

+++ georgia tech

• https://shimeng.ece.gatech.edu/downloads/

• 2017 NeuroSim+: An Integrated Device­to­Algorithm Framework for Benchmarking Synaptic Devices and Array Architectures

2017 Designing Energy-Efficient Convolutional Neural Networks using Energy-Aware Pruning

Tien-Ju Yang, Yu-Hsin Chen, Vivienne Sze

https://dfan.engineering.asu.edu/ ... detailed NeuroSim

• https://dfan.engineering.asu.edu/in-memory-computing/

• Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience

• Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach
  Shaahin Angizi and Deliang Fan

....In this paper, we review several of our recent works regarding Processing-inMemory (PIM) accelerator based on Magnetic Random Access Memory computational sub-arrays to accelerate the inference
mode of quantized neural networks using digital non-volatile memory rather than using analog crossbar operation

Mitigate Parasitic Resistance in Resistive Crossbar-based Convolutional Neural Networks FAN ZHANG, Binghamton University, USA MIAO HU